The present invention relates generally to a semiconductor memory apparatus, and more particularly, to data alignment circuit and method of a semiconductor memory apparatus.
Generally, a semiconductor memory apparatus transmits and receives multi-bit data in series using an external memory controller. On the other hand, a plurality of global data buses (GIO) are provided inside of the semiconductor memory apparatus in order to transmit multi-bit data to a core area or output multi-bit data from a core area, and the multi-bit data transmitted through the global data buses are arranged in parallel. In this manner, multi-data data is transmitted in parallel inside of the semiconductor memory apparatus but is transmitted in series outside of the semiconductor memory apparatus. Thus, a circuit for aligning serial data in parallel is required in a data input area, and a circuit for aligning parallel data in series is required in a data output area. To this end, the semiconductor memory apparatus is configured to include data alignment circuits in the data input area and the data output area.
Generally, the data alignment circuit of the semiconductor memory apparatus provided in the data input area is configured to perform synchronization of data inputted through a plurality of data pads by using a data strobe clock signal (DQS), synchronizing the data with an internal clock signal, and transferring the data to the global data buses. In a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a faster data input operation may be performed by latching data bits at rising and falling edges of the data strobe clock signal (DQS). The internal clock signal is generated from a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit and has recently been implemented in the form of a multi-phase clock signal in order to support a faster operation speed.
However, it is difficult to exactly synchronize the timing of a plurality of data transferred to data pads from outside of the semiconductor memory device, and often a slight timing difference occurs among the plurality of data. As development of the semiconductor memory apparatus is advanced to perform higher-speed operation, even a slight difference of data input timing may cause malfunction in a data alignment operation. Accordingly, a conventional data alignment circuit of a semiconductor memory apparatus should be configured in a structure for preventing such a malfunction.
FIG. 1 is a schematic configuration diagram of a conventional data alignment circuit of a semiconductor memory apparatus, illustrating a block which extracts phase information of input data.
Referring to FIG. 1, the conventional data alignment circuit of the semiconductor memory apparatus includes: a counter 1 configured to generate a counting signal CNT; a multiplexer (MUX) 2 configured to sequentially output first through eighth data DQ<1:8>; first through eighth flip-flops FF1 through FF8 configured to latch first through eighth clock signals CLK<1:8> in response to the data transferred from the multiplexer 2; an encoder 3 configured to encode output signals of the first through eighth flip-flops FF1 through FF8 and generate a 3-bit encoding signal ENC; and a register 4 configured to store the encoding signal ENC.
The first through eighth clock signals CLK<1:8> are multi-phase clock signals generated from a DLL circuit or a PLL circuit, and the clock signals are generated by dividing a phase of a single clock signal by 8. When the multiplexer 2 transfers any one of the first through eighth data DQ<1:8> to the first through eighth flip-flops FF1 to FF8, the flip-flop to which a clock signal whose phase leads the phase of the data is inputted outputs a high-level signal, and the flip-flop to which a clock signal whose phase lags behind the phase of the data is inputted outputs a low-level signal. During such a phase information extraction operation, all of the first through eighth data DQ<1:8> are controlled to have a high-level potential.
The encoder 3 is configured to encode the output signals of the first through eighth flip-flops FF1 through FF8, and transfer the encoded signals to the register 4. The register 4 is configured to store phase information of the 1-bit data. Subsequently, if the multiplexer 2, the first through eighth flip-flops FF1 through FF8, and the encoder 3 are repetitively operated, the register 4 can store phase information of the respective bits of the first through eighth data DQ<1:8>.
Subsequently, the phase information of the respective bits of the first through eighth data DQ<1:8>, which are stored in the register 4, are used to control the phases of the first through eighth data DQ<1:8> in a circuit area (not shown). In such a manner, the data alignment circuit of the semiconductor memory apparatus can support a stable data input operation by performing the operation of controlling the respective phases of the first through eighth data DQ<1:8> and aligning the first through eighth data DQ<1:8>.
However, since the above-described data alignment circuit must receive the multi-phase clock signals from the DLL circuit or the PLL circuit upon its operation, a large number of signal lines are necessarily provided in the data alignment circuit. Therefore, a disadvantage arises in that the area efficiency is degraded. Furthermore, as a complicated circuit configuration is provided for extracting the phase information of the data, the design facilitation is degraded. As such, the conventional data alignment circuit of the semiconductor memory apparatus has a technical limitation in that the occupied area is large and the design facilitation is degraded, which serves as a factor to obstruct the implementation of a high-performance semiconductor memory apparatus.